FIG. 1 shows a simplified block diagram for a computer system 20. Host processor 30 is, e.g., a microprocessor, digital signal processor, or an array of such processors. Host processor 30 connects to chipset 40 by front-side bus FSB. Chipset 40 also connects to: system memory 50 via memory bus 52; PCI peripherals 60 via PCI bus 62; a variety of I/O and/or data storage devices (not shown) via interfaces to I/O ports 70; and a graphics subsystem 80 (optional) via an Accelerated Graphics Port (AGP) bus 82. Chipset 40 may comprise a single integrated circuit or a number of separate but interconnected bridge, adapter, hub, and/or interface circuits, depending on the type and capabilities of computer system 20. Generally, however, the purpose of chipset 40 is to connect peripherals to host processor 30 and effect efficient data transactions to, from, and between its attached peripherals without burdening host processor 30 any more than necessary.
FIG. 2 shows some elements of computer system 20 in more detail. Within chipset 40, several blocks are shown. Host interface 42, memory controller 44, I/O interface 45, graphics interface 46, and PCI controller 48 communicate with their respective attached devices according to protocols, timing, and signaling understood by those attached devices. Within chipset 40, those interfaces and controllers intercommunicate in order to bridge data transactions between one interface and another interface.
Computer system 20 has a finite addressable data space that is shared by all addressable components of the system. Address decoders 43 and 49 examine transaction addresses generated by the host processor, graphics subsystem, or PCI subsystem, and then route each corresponding transaction to the addressable component assigned to that address range. For instance, physical memory may be mapped to addresses from 0 up to 2 GB (Gigabytes), the graphics subsystem may use addresses between 2 GB and 3 GB, and addresses between 3 GB and 4 GB may be allocated to PCI controller 48 and its attached peripherals. When the host issues an address, address decoder 43 compares it to these address ranges and then routes the address and corresponding host command appropriately (e.g., to memory controller 44 for addresses below 2 GB).
Chipset 40 typically maintains a set of chipset configuration registers 41 in a specific addressable location. Configuration instructions executed by host processor 30 read these configuration registers to learn and/or set the capabilities of computer system 20.
PCI controller 48 functions as a PCI-to-host bridge, and conforms to the PCI Local Bus Specification, Rev. 2.3, Oct. 31, 2001. Below controller 48, PCI BUS1 connects to PCI agents 120, 100, and 110, which have been enumerated as devices DEV1, DEV2, and DEV3. PCI agent 100 is a simple single-function device; PCI agent 110 is a multifunction device; and PCI-PCI bridge 120 provides a connection path between PCI BUS1 and PCI BUS2.
PCI bridge 120 conforms to the PCI-to-PCI Bridge Architecture Specification, Rev. 1.1, Dec. 18, 1998, which describes the behavior of a device connecting two PCI buses. Bridge 120 has a primary interface and a secondary interface. The primary interface connects to the PCI bus closest to the host (PCI BUS1); the secondary interface connects to the PCI bus further from the host. Bridge 120 is said to forward a transaction upstream when that transaction flows from the secondary to the primary interface, and downstream when that transaction flows in the opposite direction.
Each device attached to a PCI bus is required to have a PCI-defined configuration register, e.g., device CREG 101, 121, 131, 141. Multifunction devices have a configuration register for each function, e.g., FO CREG 111 and F1 CREG 112. These registers contain information useful for plug-and-play systems, and have some configurable elements used, e.g., to assign an addressable space to each device and set its behavior.
PCI controller 48 can access configuration registers in each PCI agent by placing a configuration read or write command on the bus. A type 0 configuration transaction, shown in FIG. 3a, can be issued to any device attached to PCI BUS1. The target device responds by allowing access to the Function Number, Register Number specified in the transaction address. A type 1 configuration transaction, shown in FIG. 3b, must be issued to access an agent located on PCI BUS2. Bridge 120 examines the contents of a type 1 address, and if Bus Number matches its secondary bus number, it converts the command to type 0 and places it on BUS2 to the indicated Device Number. The target device then allows access to the specified Function Number, Register Number. If the command is a configuration read, bridge 120 relays the register contents from the target device back up to controller 48.
Host processors don't typically have special configuration commands available. Therefore, host access to configuration registers relies on two registers in the chipset, CONFIG_ADDRESS register 46 and CONFIG_DATA register 47. To access PCI configuration registers, the host writes data in the format shown in FIG. 3c to CONFIG_ADDRESS. The host then initiates a memory read or write command to the CONFIG_DATA address. This read or write triggers PCI controller 48 to translate the value stored in CONFIG_ADDRESS to a type 0 or type 1 configuration address and begin the appropriate configuration cycle. FIG. 4 shows, for CONFIG_ADDRESS defined at address 0xCF8 (where 0x indicates hexadecimal notation) and CONFIG_DATA defined at address 0xCFC, how chipset 40 functions to allow a host to access PCI configuration registers.